An Integrated Switching Technique for Minimizing Power Consumption Using MDFSD in Domino Logic System

A domino logic technique is designed to meet the critical concern of the VLSI era with convenience and high microelectronic devices, power consumption of the digital circuit. The design and circuit performance improves the power consumption, area and delay of the circuit. If there is a path delay in wide fan multiplexers, then path reads out becomes more difficult and there is high power consumption due to switching activity, also it has high noise immunity in the dynamic gates. At a lower level, if the device operates with better efficiency the power consumption, speed, delay processing and power dissipation have to be sustained. To maintain the device level proposed circuit design is implemented, so that the voltage level is minimized. The designed Filtered Switch Domino (FSD), Multi Dynamic Node Domino (MDND) and measured the parameters like power, area and delay. For further improvement both the FSD and MDND were combined and results have been deliberate. The experimental setup is designed by Cadence –Virtuoso analogy tools. In domino logic circuit these techniques are proposed to improve the performance and to provide better results in power consumption than the existing methods.